Linux on RISC-V and the New OS-A Platform
Drew Fustini, BayLibre [Open Source Summit EU 2022]

RISC-V is a free, open ISA, initially defined in 2010. It doesn’t force a specific microarchitecture, so in-order, out-of-order, vector, … are possible. It’s extensible.

Base integer ISAs are RV32I (<50 instructions), RV64I, RV128I. XLEN defines register width: 32 for RV32I, 64 for RV64I. On top of these come extensions, e.g. A for atomic operations, C for compressed instructions. Linux usually targets GC. 40 new extensions were defined in 2021. Extensions are bundled in profiles (like RVA for Linux). It’s equivalent to a string of extension letters.

RISC-V has an open community that anyone (individuals, companies, non-profits) can join. There are meetings in western and asian timezones.

RISC-V is just a specification. There are open-source and proprietary implementations. e.g. Rocket and BOOM from Berkeley. OpenHW group creates open source proven hard IP called Core-V.

Software ecosystem is already well developed: Linux, BSD, FreeRTOS, Zephyr, gcc, glibc, gdb, binutils, clang, v8/NodeJS, Rust, Go, OpenJDK, Python.

Privileged architecture defines User (U), Supervisor (S) and Machine (M) mode. The ECALL instruction transfers control to a higher privilege.

Control and Status registers (different per mode) have specific instructions to access.

Virtual memory has up to 5 level page table for 57-bit physical addresses.

Trap handling for exceptions and interrupts.

Hart is a hardware thread, i.e. SMT. It means an independent instruction fetch unit. Linux sees it as a separate core.

There are two interrupt controllers: PLIC (Platform Level Interrupt Controller) is global, CLINT (Core Local Interrupt) is local per hart. Recently replaced with APLIC (Advanced PLIC) and IMSIC (Incoming Message-Signaled Interrupt Controller) for PCIe, ACLINT (advanced CLINT).

SoC starts in Boot ROM in M Mode. First stage bootloader runs in this mode. This hands off to SBI, Supervisor Binary Interface, which eventually hands off to U-Boot in S mode. It’s an ABI allowing OSes to access M mode services. SBI is the interface specification, OpenSBI is an implementations. It does the boot flow and also provides runtime services. SBI has again several extensions: base, timer, IPI, RFENCE. Recently also hart state managmeent to suspend harts, system reset, performance monitoring.

Hypervisor Supervisor and Virtualized Supervisor mode are additional (extension) modes that sit between S and M mode.

OpenSBI used to be compiled differently for each platform, but now this has changed that SPL hands off a DTB to OpenSBI instead.

UEFI support is provided by U-Boot and EDK2. Grub2 and Linux itself can be used as a UEFI payload. Originally, the boot hart ID was passed in a register, but this had to change for UEFI support.

RISC-V Platofmr Specification will allow a generic a distro to specify what kind of platform it can run on, and a platform to specify what kind of platform it is, so compatibility between the two can be checked. Several platforms defined for different purposes. Platform spec includes the ISA profile, debug, timer interrupt, calling conventions, ABI, … OS-A Embedded Platform uses EBBR boot spec from ARM. For OS-A Server platform, the hardware is expressed in ACPI. Some new tables are needed to support RISC-V, for hart capabilities and for timers.

It’s supported in Fedora, Debian, Ubuntu, OpenSuSE, Arch, Gentoo to some level.

One of the off-the-shelf available SoCs is the Allwinner D1 SoC with T-Head core that is based on an earlier ARM SoC with just the CPU swapped to RISCV, which means most of the drivers are already available. However, it uses a non-standard MMU which requires special support in the kernel. Fortunately, there are patches on the way upstream that can deal with both type of MMU with runtime selection (without overhead). Similar issue exists for cache flush instructions and could be solved in the same way.

Because it’s an open spec, anyone can propose changes to the spec. However, this creates a challenge: people want to test their extensions-in-development so they want support for it in Linux, but Linux doesn’t want to merge it if it’s not actually ending up in the spec. Some guideline has been defined to decide what to accept.

We can expect RPi-like boards (but a bit more expensive for now) next year. There are D1 based boards for about $50. Vision-V targets a 4-core SoC board for <$100.

Talk went really fast, please check the slides for more info.